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Device Overview S12XS Family
1.3
System Clock Description
The clock and reset generator module (CRG) provides the internal clock signals for the core and all
peripheral modules. Figure 1-6 shows the clock connections from the CRG to all modules.
Consult the S12XECRG section for details on clock generation.
NOTE
The XS family uses the XE family clock and reset generator module.
Therefore all CRG references are related to S12XECRG.
SCI0 . . SCI 1
SPI0
CAN0
ATD0
Bus Clock
PIT
EXTAL
Oscillator Clock
TIM
CRG
XTAL
Core Clock
PIM
PWM
RAM
S12X
FLASH
Figure 1-6. Clock Connections
The system clock can be supplied in several ways enabling a range of system operating frequencies to be
supported:
? The on-chip phase locked loop (PLL)
? the PLL self clocking
? the oscillator
S12XS Family Reference Manual, Rev. 1.13
48
Freescale Semiconductor
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